Embedded Calculators & Part Finder

Enter two or more component values separated by commas. The equivalent uses the same unit as the inputs.

• Resistors / Inductors — Series: R = R₁ + R₂ + … · Parallel: 1/R = 1/R₁ + 1/R₂ + …
• Capacitors (reversed) — Series: 1/C = 1/C₁ + 1/C₂ + … · Parallel: C = C₁ + C₂ + …

When you need it: Reducing a network of resistors, capacitors or inductors to a single equivalent value when hitting a non-standard value or checking a combination.

Worked example: Two 10 kΩ in parallel = 5 kΩ; in series = 20 kΩ. Capacitors are the mirror image: two 100 nF in series = 50 nF, in parallel = 200 nF. Parallel resistors follow 1/Rt = Σ 1/Ri.

Tips & gotchas:

• Resistors and inductors combine the same way (series adds); capacitors are reversed (parallel adds).
• N equal values in parallel give value/N — a quick way to make an odd value from stock parts.
• A parallel resistance is always smaller than the smallest resistor in the group.
• Paralleling to hit a value multiplies your tolerance error — two 5% parts don't make a 1% result.

For resistors in parallel, each branch current is: I_k = Iin × (1/R_k) / Σ(1/R_i).

Usage: Enter the total current and two or more branch resistances; the currents always sum back to Iin.

When you need it: Finding how a current splits between parallel branches — sizing a shunt, balancing parallel LED strings, or checking how paralleled resistors share a load.

Worked example: 10 mA into 100 Ω ∥ 300 Ω: the 100 Ω branch takes 10mA × 300/(100+300) = 7.5 mA and the 300 Ω branch takes 2.5 mA — more current flows through the smaller resistor.

Tips & gotchas:

• Current splits inversely to resistance — the opposite of how a voltage divider splits voltage.
• For two branches, one branch gets Itotal × (Rother / (R1 + R2)); note it's the other resistor on top.
• All branches must share the same two nodes for the formula to hold.
• Tolerance mismatch makes parallel devices share unevenly — a real concern for paralleled MOSFETs or diodes.

A crystal needs its two load caps to present the rated CL: CL = (C1·C2)/(C1+C2) + Cstray. With C1 = C2: C = 2·(CL − Cstray).

Usage: Enter the crystal's datasheet load capacitance and your board's stray; use NP0/C0G capacitors of the resulting value.

When you need it: Choosing the two load capacitors for a crystal so the oscillator starts reliably and runs on frequency, accounting for the board's stray capacitance.

Worked example: For a crystal specified at CL = 12 pF with ~5 pF of stray, each load cap is Cx = 2 × (CL − Cstray) = 2 × (12 − 5) = 14 pF, one from each crystal pin to ground.

Tips & gotchas:

• Wrong load capacitance pulls the frequency off by ppm — a common cause of clocks that are "almost" right.
• Include the ~3–5 pF of pin and PCB stray capacitance in the sum, not just the caps you place.
• Too much load can stop start-up or push the crystal's ESR margin past the drive level.
• Keep the oscillator traces short and guarded with ground; it's a high-impedance, noise-sensitive node.

Wheeler's single-layer air-core approximation: L[µH] = d²·N² / (18d + 40l) (d, l in inches; converted from mm internally).

Usage: Enter coil diameter, winding length, and turns. For tightly wound coils keep length > 0.4·diameter for best accuracy.

When you need it: Estimating a single-layer air-core coil's inductance from its turns and dimensions for an RF tank, matching network or filter.

Worked example: Wheeler's formula L(µH) ≈ (d²N²)/(18d + 40l) with d and l in inches; a 0.5″ diameter, 20-turn, 1″-long coil comes out to about 1.4 µH.

Tips & gotchas:

• Air-core avoids core saturation and loss, but needs more turns than a ferrite-cored coil for the same L.
• Close-wound versus spaced windings changes the inductance — spacing lowers it.
• Distributed capacitance gives a self-resonant frequency; above it the coil looks capacitive.
• For RF-critical values, confirm with an LCR meter or VNA — formula error runs several percent.

Tj = Ta + P × θJA. Max power for a limit: Pmax = (Tjmax − Ta) / θJA.

Usage: Use the datasheet θ_JA. If margin is negative, you need a heatsink (lower θ), less power, or lower ambient.

When you need it: Computing a part's junction temperature from its power dissipation and the thermal-resistance chain, to keep it safely below Tj(max).

Worked example: P = 1 W, θJA = 50 °C/W, Ta = 25 °C → Tj = 25 + 1 × 50 = 75 °C. With a heatsink the path becomes Tj = Ta + P × (θJC + θCS + θSA).

Tips & gotchas:

• Datasheet θJA assumes a specific board copper area and airflow — treat it as optimistic.
• For SMD parts the copper pour is the heatsink; more area and thermal vias lower θJA.
• Derate to about 80% of Tj(max) for lifetime; electrolytics and plastics age fast when hot.
• The interface (thermal pad/grease, θCS) often dominates — a dry or air-gapped joint wrecks the budget.

bit period = 1/SCK, frame time = bits/SCK, throughput = SCK (1 bit per clock).

When you need it: Confirming an SCK frequency the slave can accept, and checking that setup/hold plus trace flight-time still leave a valid sampling window at high clock rates.

Worked example: SCK = 10 MHz → bit period 100 ns; a 24-bit frame takes 24 × 100 ns = 2.4 µs and throughput is 10 Mbit/s (one bit per clock). Push to 50 MHz over 15 cm of FR-4 (~1 ns each way) and the round-trip flight time starts eating the read window.

Tips & gotchas:

• At high SCK the slave's output-valid time plus trace delay can force a lower clock or a delayed sampling phase.
• CPOL/CPHA (SPI mode) must match on both ends, or every byte is shifted/inverted.
• Add series (source) termination on SCK for long traces to tame ringing and overshoot.
• Respect CS-to-first-clock setup and last-clock-to-CS hold; many slaves latch on the CS edge.

max length ≈ min(1200 m, 10⁸/baud), termination = 120 Ω each end, fail-safe bias each = 150·Vcc − 30 Ω (≥200 mV idle).

When you need it: Sizing termination, stub length and the node/distance budget for a multidrop industrial link (Modbus, DMX, building automation) so reflections and loading don't corrupt data.

Worked example: 32 standard unit-load transceivers on 120 Ω cable are terminated with 120 Ω at each far end only. Rate and reach trade off along a roughly constant product: about 100 kbit/s at 1200 m down to ~10 Mbit/s at ~12 m.

Tips & gotchas:

• Terminate only the two physical ends of the trunk — a terminator in the middle just wastes drive current and worsens loading.
• Keep stubs (drops) shorter than ~1/10 of the signal rise-time length, or they act as reflective transmission lines.
• Add fail-safe bias resistors so an idle (undriven) bus reads a defined logic level instead of noise.
• The standard driver handles 32 unit loads; use 1/8-UL transceivers to reach 256 nodes on one segment.

Frame bits = 43 + 10·N (13 break + 10 sync + 10 PID + 10·N data + 10 checksum). break = 13/baud.

When you need it: Budgeting frame time and bus load for a LIN schedule table in automotive body electronics (mirrors, seats, HVAC flaps) where a master polls low-cost slaves.

Worked example: At 19200 bit/s, an 8-data-byte frame is roughly the header (~34 bit-times) plus response (8 bytes + checksum ≈ 90 bit-times) ≈ 124 bit-times ≈ 6.5 ms nominal. Allowing the spec's up-to-40% inter-byte space, budget about 9 ms per slot.

Tips & gotchas:

• LIN tolerates roughly ±14% slave clock deviation, which is exactly why RC-oscillator nodes work without a crystal.
• Maximum bit rate is 20 kbit/s; there is no high-speed LIN.
• Keep the sum of all frame slots inside the schedule-table period, including the worst-case inter-byte spacing.
• The break field must be at least 13 dominant bit-times so every slave detects frame start.

char = 11/baud; t1.5 = 1.5·char, t3.5 = 3.5·char (fixed 750 µs / 1.75 ms above 19200 baud).

When you need it: Computing the 3.5-character inter-frame silence and the per-transaction time so you can set a realistic master poll rate and response timeout on a Modbus RTU line.

Worked example: At 9600 bps, 8N1 is 11 bits/char → 1 char = 11 / 9600 = 1.146 ms. The frame gaps are t3.5 = 3.5 × 1.146 = 4.01 ms silence between frames and t1.5 = 1.72 ms intra-frame. Reading 10 registers (~8-byte request, ~25-byte reply) totals roughly 38 ms plus the silences.

Tips & gotchas:

• Above 19200 bps the spec fixes the gaps at t3.5 = 1.75 ms and t1.5 = 750 µs instead of scaling with baud.
• Set the master's response timeout well above the slowest slave's turnaround, or you'll log false timeouts under load.
• RTU relies on exact byte framing — any gap longer than t1.5 mid-frame is treated as a frame boundary and corrupts the message.
• Use Modbus ASCII only where character gaps can't be guaranteed; it doubles the bytes on the wire.

bytes = throughput × latency × safety. Power-of-2 size lets DMA wrap with a cheap mask.

When you need it: Sizing a circular buffer for UART or ADC DMA so it never overruns between the intervals when your code drains it, and picking a power-of-two length for cheap wraparound.

Worked example: A UART at 115200 bps (~11.5 KB/s) serviced every 10 ms must hold at least 0.010 × 11520 ≈ 115 bytes per interval; round up to 256 for margin. Fill level is (head − tail) & (size − 1).

Tips & gotchas:

• A power-of-two size lets you wrap with & (N−1) instead of an expensive modulo.
• Keep one slot empty (or a separate count) so you can tell "full" from "empty" — both otherwise show head == tail.
• Single-producer/single-consumer is lock-free if head and tail are word-aligned volatile and updated last.
• Size for the worst-case service latency (ISR blocked, higher-priority task), not the average.

Each field gets NAME_SHIFT (bit offset) and NAME_MASK = ((1<<width)−1)<<offset, plus a packed bitfield struct.

When you need it: Turning a datasheet register table into C — generating #define mask/shift pairs or a bitfield struct so your driver reads and writes peripheral fields by name instead of magic numbers.

Worked example: A field MODE at bits [2:1] generates #define MODE_Pos 1 and #define MODE_Msk (0x3<<1); you set it with reg = (reg & ~MODE_Msk) | ((val<<MODE_Pos) & MODE_Msk).

Tips & gotchas:

• Generated masks survive datasheet revisions far better than hand-typed hex constants.
• Mark the register pointer volatile so field writes aren't optimised away or reordered.
• Use read-modify-write and leave reserved bits as read, never blindly zeroed.
• A packed bitfield struct is convenient but its bit ordering is implementation-defined — masks are more portable across compilers.

Emits a 256-entry lookup table and a crcN_compute() function. The Check value is the CRC of ASCII "123456789" — the standard self-test constant for verifying an implementation.

When you need it: Adding integrity checks to firmware or a serial protocol — generating a ready table-driven or bitwise CRC routine (CRC-8/16/32) that matches the polynomial the other end expects.

Worked example: CRC-16/CCITT uses poly 0x1021, init 0xFFFF; a 256-entry table costs 512 bytes of flash for roughly 8× the speed of the bit-at-a-time loop. As a sanity check, CRC-32 of the ASCII string "123456789" is 0xCBF43926.

Tips & gotchas:

• Poly, init, reflect-in, reflect-out and xor-out must all match the other end exactly, or every check fails.
• Table-driven for throughput; bitwise (or nibble-table) when flash is tight.
• A CRC detects accidental errors — it is not a cryptographic hash and offers no tamper protection.
• Always validate a new implementation against a published check value before trusting it in the field.

BCLK = fs × bits × channels, LRCLK = fs. MCLK is usually 256·fs.

When you need it: Deriving the I2S bit clock (BCLK), word-select/frame clock (WS/LRCK) and master clock (MCLK) for an audio codec from the sample rate and bit depth during audio bring-up.

Worked example: 48 kHz, 24-bit stereo in 32-bit slots → BCLK = fs × bits × channels = 48000 × 32 × 2 = 3.072 MHz, WS = fs = 48 kHz, and a typical MCLK = 256 × fs = 12.288 MHz.

Tips & gotchas:

• Many codecs require MCLK at a fixed multiple of fs (256× or 384×) — check the datasheet before picking a PLL setting.
• The slot width (often 32 bits) must be at least the audio bit depth; WS toggles once per stereo frame at fs.
• Clock jitter turns into audible artifacts — derive the audio clocks from a clean fractional-N PLL or dedicated audio oscillator.
• Match the frame format (I2S vs left-justified vs right-justified) on both the controller and the codec, or channels swap or shift.

bit time = 1/rate. USB 2.0: one D+/D− pair, 90 Ω differential; FS/LS use ~22 Ω series, HS uses 45 Ω-to-GND termination. USB 3.x SuperSpeed: separate SSTX/SSRX pairs, 90 Ω differential, AC-coupled (~100 nF in series) and receiver-terminated — no series resistor. Gen1 = 5 Gbps, Gen2 = 10 Gbps.

When you need it: Checking bit time, differential impedance and trace length-matching when routing USB 2.0 High-Speed (480 Mbit/s) or USB 3.x SuperSpeed pairs on a PCB.

Worked example: USB 2.0 HS bit time is 1 / 480e6 = 2.08 ns; route D+/D− as a 90 Ω differential pair, length-matched within a few millimetres. USB 3.0 at 5 Gbit/s has a 200 ps bit, so low-loss laminate and tight skew matter far more.

Tips & gotchas:

• Keep D+/D− (and each SuperSpeed pair) tightly coupled, length-matched, and free of stubs or unnecessary vias.
• USB 3.x SuperSpeed pairs are AC-coupled — place the series blocking caps on the transmit side and match the pair skew.
• Put ESD protection and, if needed, a common-mode choke right at the connector, not deep in the board.
• Reference the pair over a continuous ground plane; a plane split under the pair wrecks the impedance and radiates.

bit time = 1/rate; propagation delay ≈ 5 ns/m (NVP ≈ 0.66). Standard segment limit is 100 m.

When you need it: Checking maximum cable reach, pair-to-pair delay skew and PoE voltage drop for 10/100/1000BASE-T runs before committing a cable spec.

Worked example: A Cat5e 100BASE-TX channel is capped at 100 m (90 m solid horizontal + 10 m patch); 1000BASE-T uses all four pairs. The loop resistance of 100 m of Cat5e is about 2 × 9.38 = 18.8 Ω, so PoE at 0.36 A drops roughly 0.36 × 18.8 ≈ 6.8 V along the run.

Tips & gotchas:

• The 100 m channel limit holds regardless of speed — it's a timing/attenuation budget, not just resistance.
• For Gigabit keep pair-to-pair delay skew under ~50 ns; the PHY de-skews the four pairs but only within a window.
• Use Cat6/6A for 10GBASE-T, and keep bundles loose to limit alien crosstalk at 10G.
• Size PoE for worst-case cable resistance and temperature; copper resistance rises ~0.4%/°C.

steps/rev = 360 / step angle; microsteps = steps × microstep factor; pulse rate = microsteps/rev × RPM / 60.

When you need it: Working out steps per revolution, speed and linear travel for a stepper with microstepping and, often, a leadscrew.

Worked example: A 1.8° motor is 200 full steps/rev; at 16× microstepping that's 3200 steps/rev. On an 8 mm-pitch screw, one microstep moves 8 / 3200 = 2.5 µm.

Tips & gotchas:

• Torque drops with speed as back-EMF rises — check the motor's speed-torque curve, not just the holding torque.
• Microstepping smooths motion but doesn't add real accuracy; friction and detent torque dominate positioning.
• Step rate = speed × steps/rev; make sure your driver and MCU can sustain the pulse rate.
• Use acceleration/deceleration ramps — commanding full speed instantly stalls or skips steps.

f_elec (Hz) = RPM × pole pairs / 60; electrical RPM = RPM × pole pairs. 6-step commutation = pole pairs × 6 per mechanical rev.

When you need it: Relating electrical drive frequency, pole count and mechanical RPM for a brushless motor, and using Kv to predict no-load speed from supply voltage.

Worked example: RPM = 120 × f / poles, so an 8-pole motor at 100 Hz electrical spins 120 × 100 / 8 = 1500 RPM. No-load speed ≈ Kv × Vsupply.

Tips & gotchas:

• Mechanical RPM equals the electrical frequency divided by the number of pole pairs, not poles.
• Kv and the torque constant are inverses — a high-Kv motor spins fast but makes less torque per amp.
• Field weakening pushes speed above the base value at the cost of available torque.
• Commutation needs rotor position from Hall sensors, an encoder, or a sensorless back-EMF estimator.

P (W) = T (N·m) × ω, ω = 2π·RPM/60. Equivalently T = 9.5493 × P / RPM. 1 hp = 745.7 W.

When you need it: Converting between torque and mechanical power at a given speed when sizing a motor, gearbox or the load it drives.

Worked example: P(W) = τ(N·m) × ω(rad/s) = τ × RPM × 2π/60. So 0.5 N·m at 3000 RPM is 0.5 × 314 ≈ 157 W.

Tips & gotchas:

• Power is torque × angular speed, so a small fast motor can match a big slow one on power alone.
• A gearbox trades speed for torque by the ratio (minus its efficiency) — reduce speed, multiply torque.
• Distinguish continuous from peak torque ratings; sustained operation must stay under the continuous figure.
• Add inertia (acceleration) torque for dynamic loads on top of the steady-state requirement.

counts/rev = PPR × decoding; resolution = 360 / counts/rev; count rate = counts/rev × RPM / 60.

When you need it: Working out counts per revolution, angular resolution and speed from an incremental encoder using quadrature decoding.

Worked example: A 1024 PPR encoder with 4× quadrature gives 4096 counts/rev → resolution = 360 / 4096 = 0.088°. Speed in RPM is (counts/s) × 60 / counts_per_rev.

Tips & gotchas:

• 4× quadrature decoding quadruples resolution for free by counting every edge of both channels.
• The index (Z) pulse gives one absolute home reference per revolution for zeroing.
• Maximum count rate limits top speed — watch the hardware timer or interrupt load at speed.
• Differential (RS-422) outputs survive noise on long cables far better than single-ended ones.

P_cond = Irms² × Rds(on); P_sw ≈ ½ × Vds × I × (tr+tf) × fsw. Total dissipation sets the heatsink/θJA requirement.

When you need it: Budgeting a MOSFET's conduction and switching losses to choose the part and heatsink for a switching converter or a load switch.

Worked example: Rds(on) = 20 mΩ, Irms = 5 A → conduction loss = I²R = 0.5 W. Switching loss ≈ ½ × Vds × Id × (tr + tf) × fsw; at 24 V, 5 A, 50 ns, 100 kHz that's ~0.3 W, so ~0.8 W total.

Tips & gotchas:

• Conduction loss dominates at low switching frequency; switching loss dominates at high frequency.
• Rds(on) rises with temperature (~1.4× at 100 °C) — use the hot value, not the 25 °C figure.
• Gate-drive strength sets tr/tf; a weak driver quietly multiplies switching loss.
• Add gate-charge loss Qg × Vgs × fsw and the body-diode/reverse-recovery loss in hard-switched legs.

Vp/Vs = Np/Ns = Is/Ip = n. An ideal transformer conserves power: Vp·Ip = Vs·Is.

When you need it: Finding the turns ratio for a target voltage, or the impedance a load reflects to the primary, in a mains, audio, isolation or flyback transformer.

Worked example: 120 V→12 V gives Np/Ns = 10. Impedance reflects as the square of the ratio: an 8 Ω load through a 10:1 winding looks like 8 × 10² = 800 Ω at the primary.

Tips & gotchas:

• Voltage scales with the turns ratio; impedance scales with the ratio squared.
• The core must reset its volt-seconds each cycle or it walks into saturation and the current spikes.
• Real windings add resistance and leakage inductance — they cap efficiency and cause ringing.
• In a flyback the ratio also sets the switch's reflected voltage stress, so it's a safety-margin knob too.

P = (Vin−Vout)·Iload + Vin·Iq; efficiency ≈ Vout/Vin. Dropout headroom must exceed the regulator's spec.

When you need it: Checking whether an LDO has enough headroom to stay in regulation, and how hot it runs, at your input voltage and load current.

Worked example: 5 V→3.3 V at 200 mA dissipates (5 − 3.3) × 0.2 = 0.34 W. In a SOT-23 (θJA ≈ 200 °C/W) that's a 68 °C rise — near the limit, so use a larger package or a buck pre-regulator.

Tips & gotchas:

• LDO efficiency is just Vout/Vin — the rest becomes heat, so keep Vin close to Vout.
• Respect the dropout voltage at your maximum current, or the output sags out of regulation.
• Output-capacitor ESR requirements vary — some LDOs need a minimum ESR, others demand low ESR; check the datasheet.
• For a big step-down at high current, a switching regulator wastes far less power than any LDO.

Γ = (VSWR−1)/(VSWR+1); RL = −20·log₁₀|Γ| dB; ML = −10·log₁₀(1−Γ²) dB; reflected power = Γ².

When you need it: Quantifying an impedance mismatch on an RF line — converting between VSWR, return loss, reflection coefficient and the fraction of power bounced back.

Worked example: Γ = 0.2 → VSWR = (1 + 0.2)/(1 − 0.2) = 1.5 and return loss = −20·log₁₀(0.2) = 14 dB. A 2:1 VSWR (~9.5 dB RL) reflects about 11% of the incident power.

Tips & gotchas:

• Lower VSWR means a better match — 1:1 is ideal; higher numbers mean more reflection.
• Mismatch (transmission) loss is small even at VSWR 2 (~0.5 dB); reflections matter more for amplifier stability and hot spots.
• Return loss is quoted as a positive dB figure — how far the reflected wave sits below the incident.
• Match is frequency-dependent; measure at the band of interest, not just at one spot frequency.

Prx = Ptx + Gtx + Grx − FSPL − Lother; margin = Prx − sensitivity. A positive margin (typ. >10 dB) means the link closes.

When you need it: Estimating received power and link margin over a wireless path from transmit power, antenna gains and path loss — the go/no-go check for a radio range.

Worked example: Prx = Ptx + Gtx + Grx − FSPL = 10 + 2 + 2 − 90 = −76 dBm. If the receiver sensitivity is −95 dBm, the link margin is 19 dB.

Tips & gotchas:

• Aim for at least 10–20 dB of fade margin; free-space path loss is a best case that real environments never quite hit.
• Add clutter, multipath and rain/foliage losses on top of FSPL for a realistic budget.
• Cable, connector and mismatch losses at each end come straight off the margin.
• Doubling frequency adds 6 dB of path loss for the same distance — a real cost of going higher in band.

λ = c / f × VF, c = 299.792458 m·MHz. A half-wave dipole ≈ λ/2; a quarter-wave whip ≈ λ/4.

When you need it: Sizing an antenna element (quarter-wave whip, half-wave dipole) or a matching stub from frequency, including the velocity/shortening factor of real conductors.

Worked example: At 433 MHz, λ = c/f = 0.693 m, so a quarter-wave whip is λ/4 ≈ 173 mm; apply a ~0.95 velocity factor for wire and it trims to about 164 mm.

Tips & gotchas:

• Always apply the velocity factor — ~0.95 for wire, ~0.66–0.85 for coax — or the element runs long.
• A monopole needs a ground plane; its size and shape shift the resonance and pattern.
• A quarter-wave element also resonates at odd harmonics (3×, 5× the frequency).
• Trim to resonance with a VNA; nearby metal and enclosure loading detune a "calculated" length.

A Wheatstone bridge measures small resistance changes (strain gauges, RTDs) as a differential voltage.

• Output: Vout = Vin·(R2/(R1+R2) − R4/(R3+R4))
• Balance (Vout = 0): R1/R2 = R3/R4, so R4 = R3·R2/R1

Usage: Set the excitation and the three fixed arms; the unbalanced output is the sensor signal — usually fed to an instrumentation amplifier.

When you need it: Reading a small resistance change from a strain gauge, RTD or pressure sensor as a differential voltage out of a balanced bridge.

Worked example: With one active arm, the output is Vex × (ΔR/R) / 4. A 5 V excitation and a 0.1% resistance change gives 5 × 0.001 / 4 = 1.25 mV — small enough that it needs an instrumentation amplifier.

Tips & gotchas:

• Two or four active arms multiply sensitivity and cancel common-mode temperature drift.
• Keep the excitation stable, or measure ratiometrically against it, so supply drift doesn't look like signal.
• Lead resistance matters for remote sensors — use 3- or 4-wire RTD connections.
• The signal is millivolts; a low-offset, high-CMRR in-amp is essential to see it cleanly.

A resistive pad reduces signal level by a fixed amount while keeping the line matched to Z₀. Let K = 10^(dB/20).

• T-pad: R1 = Z₀(K−1)/(K+1), R2 = Z₀·2K/(K²−1)
• Pi-pad: R1 = Z₀(K+1)/(K−1), R2 = Z₀(K²−1)/(2K)

Usage: Enter the attenuation and system impedance (50 Ω for most RF). Pick the T or Pi topology that gives the most buildable resistor values.

When you need it: Designing a matched resistive pad that drops signal level by a set number of dB while keeping the line at its characteristic impedance (usually 50 Ω).

Worked example: A 6 dB 50 Ω Pi pad uses a series R ≈ 37 Ω between two shunt Rs ≈ 150 Ω. The voltage ratio is 10^(dB/20), and the pad presents 50 Ω at both ports.

Tips & gotchas:

• Resistive pads are broadband and dead simple, but they dissipate the attenuated power as heat.
• T topology suits low attenuation; Pi is common at 50 Ω — both are matched two-ports.
• The input resistor sees the most power; rate it for the full input level at high drive.
• A pad also improves source/load match — a few dB of padding is a cheap VSWR fix.

LM317 sets its output by holding Vref (≈1.25 V) across R1, so the divider R1/R2 programs Vout.

• Output: Vout = Vref × (1 + R2/R1) + Iadj × R2
• Required R2: R2 = (Vout − Vref) / (Vref/R1 + Iadj)

Usage: Keep R1 ≈ 240 Ω, set R2 for the voltage you need, or type a Target Vout to get the exact R2. Minimum Vout = Vref (1.25 V).

When you need it: Setting an adjustable linear regulator's output with two resistors, or wiring it as a simple constant-current source for an LED string or battery charger.

Worked example: Vout = 1.25 × (1 + R2/R1); with R1 = 240 Ω, R2 = 720 Ω → 1.25 × (1 + 3) = 5.0 V. As a current source, I = 1.25 / R.

Tips & gotchas:

• Keep the standard R1 ≈ 240 Ω so the regulator's minimum load current is always met.
• Dissipation is (Vin − Vout) × I — a large drop at high current needs a real heatsink.
• It needs roughly 2.5–3 V of headroom (dropout); an LDO is better when Vin is close to Vout.
• Add the datasheet protection diodes when using large output or adjust-pin capacitors.

IEEE 754 is the technical standard for floating-point computation established by the IEEE in 1985.

Layout Specifications:

• Single Precision (32-bit): 1 sign bit [31], 8 exponent bits [30-23] (bias = 127), 23 fraction bits [22-0].
• Double Precision (64-bit): 1 sign bit [63], 11 exponent bits [62-52] (bias = 1023), 52 fraction bits [51-0].

Special Cases:

• Zero: Exponent = 0, Fraction = 0
• Denormalized (Subnormal): Exponent = 0, Fraction ≠ 0. Value is (-1)^S × 0.F × 2^1-bias.
• Infinity: Exponent = All 1s (255 or 2047), Fraction = 0
• NaN (Not a Number): Exponent = All 1s, Fraction ≠ 0

When you need it: Debugging why a float comparison fails, reading a float out of a raw memory dump, or understanding precision loss when porting math to a 32-bit MCU.

Worked example: 0.1f is stored as 0x3DCCCCCD ≈ 0.100000001 — not exact, which is exactly why 0.1 + 0.2 ≠ 0.3. A float32 is 1 sign bit, 8 exponent bits (bias 127), and 23 mantissa bits.

Tips & gotchas:

• Never compare floats with ==; test |a − b| < epsilon instead.
• NaN is never equal to anything, including itself — use it to detect it (x != x).
• float32 carries ~7 significant decimal digits, float64 ~15; pick the width your dynamic range needs.
• Watch byte order when reading floats from a dump — the four bytes are stored little-endian on most MCUs.

PWM (Pulse Width Modulation) is used to control power delivery by switching a digital signal on and off rapidly.

Formulas:

• Edge-Aligned Mode: f = Clock / ((PSC + 1) * (ARR + 1))
• Center-Aligned Mode: f = Clock / ((PSC + 1) * 2 * (ARR + 1))
• Duty Cycle %: (CCR / (ARR + 1)) * 100

Usage: Enter your MCU's timer clock frequency, select the alignment mode, and set the Prescaler and Period Count to calculate the resulting PWM frequency and resolution.

When you need it: Setting an LED dimming or motor-drive frequency, generating a servo pulse, or synthesising an analog voltage by low-pass filtering the output. On an MCU the real task is picking a timer prescaler (PSC) and auto-reload (ARR) that hit your target frequency, then a compare value (CCR) for the duty.

Worked example: A 72 MHz timer clock targeting 20 kHz PWM needs ARR + 1 = 72e6 / 20000 = 3600, so PSC = 0, ARR = 3599. For 25% duty, CCR = 0.25 × 3600 = 900. The available duty resolution is timer_clk / f = 3600 steps (~11.8 bits).

Tips & gotchas:

• Resolution and frequency trade off: at a fixed timer clock, doubling the PWM frequency halves the number of duty steps.
• Higher frequency reduces audible whine and output ripple but raises switching losses in the driver/MOSFET.
• Use center-aligned mode for motor drive (symmetric edges, lower harmonics) and insert dead-time on complementary half-bridge outputs.
• To make an analog voltage, size the RC filter so fc ≪ f_PWM; ripple falls ~20 dB/decade below the PWM frequency.

UART (Universal Asynchronous Receiver-Transmitter) requires both devices to agree on a baud rate within tight timing tolerances.

Formulas:

• Exact Baud Rate: Baud = Clock / (Oversampling * USART_DIV)
• Error %: ((Actual - Target) / Target) * 100
• Frame Time: (Data + Parity + Stop + Start bits) / Baud

Usage: Input the system clock and target baud rate. An error rate of ≤ 0.5% is excellent, ≤ 2% is acceptable, and anything above 2% may cause data corruption.

When you need it: Choosing a baud rate the MCU's clock can actually generate within tolerance, or diagnosing garbled bytes that come from too much baud error between two devices.

Worked example: 16 MHz clock, 115200 baud, 16× oversampling → USARTDIV = 16e6 / (16 × 115200) = 8.68. Rounding to 9 gives an actual 16e6 / (16 × 9) = 111111 baud, an error of (111111 − 115200) / 115200 = −3.5% — over budget. A fractional baud generator or 8× oversampling closes the gap.

Tips & gotchas:

• Keep total baud error under about ±2%; a UART samples mid-bit and accumulates error across ~10 bits per frame, so ±2.5% is roughly the breaking point.
• Both ends must agree within their combined tolerance — a −1.5% transmitter and +1.5% receiver already eat the whole margin.
• Fractional (fixed-point) baud dividers on modern MCUs cut the error dramatically versus integer-only dividers.
• High baud rates (≥ 921600) need a clean crystal-derived clock; internal RC oscillators drift with temperature and voltage.

ADC (Analog-to-Digital Converter) translates continuous analog voltages into discrete digital steps.

Formulas:

• LSB (Step Size): Vref / 2^Resolution
• Theoretical SNR: 6.02 * Resolution + 1.76 dB
• Conversion Time: (Sampling Cycles + SAR Cycles) / ADC_Clock

Usage: Use this calculator to find the voltage resolution (LSB) and conversion time for your MCU. Higher oversampling improves effective resolution (ENOB) at the cost of conversion speed.

When you need it: Working out the smallest voltage an ADC can resolve (one LSB), estimating the ideal signal-to-noise ratio, or choosing how many bits you need to cover a sensor's range with margin.

Worked example: A 12-bit ADC with Vref = 3.3 V has LSB = 3.3 / 4096 = 0.806 mV. Its ideal SNR is 6.02 × 12 + 1.76 = 74 dB, and a 10 mV signal spans about 10 / 0.806 ≈ 12 codes.

Tips & gotchas:

• Effective number of bits (ENOB) is always below the nominal count once you include noise, INL/DNL and reference error — treat the datasheet's ENOB, not the bit count, as real resolution.
• Oversampling and averaging buys ~½ extra bit per 4× samples, but only if there is at least 1 LSB of noise to dither against.
• Give the sample-and-hold enough acquisition time for your source impedance, or the reading droops; add a small buffer/cap for high-impedance sensors.
• Ratiometric measurement (sensor and ADC share the same reference) cancels Vref drift entirely.

Bit Field Visualizer breaks down 32-bit registers into readable binary grids, allowing engineers to quickly inspect register values.

Formulas:

• Value: Sum(Bit_i * 2^i)

Usage: Input a hexadecimal register value. Click any bit in the grid to toggle it. The decimal, binary, and C macro initialization code will update instantly.

When you need it: Laying out or decoding an MCU peripheral register — packing flags and multi-bit fields into one word, or reading a hex value back into named fields while bringing up a driver.

Worked example: A control register with EN[0], MODE[2:1], PRESCALER[7:4]. To set EN=1, MODE=2, PRESCALER=3 → (1<<0) | (2<<1) | (3<<4) = 0x35. Reading it back, PRESCALER = (0x35 >> 4) & 0xF = 3.

Tips & gotchas:

• Read with mask-after-shift: (v >> pos) & mask; write with read-modify-write and clear the field first.
• Declare memory-mapped registers volatile so the compiler doesn't cache or reorder accesses.
• Read-modify-write on a register shared with an ISR is a race — disable the interrupt or use bit-banding/atomic set-clear registers.
• Preserve reserved bits: read them, keep their value, and don't blindly write zeros.

Q-Format Fixed-Point represents fractional numbers using pure integers, which is vital for high-speed DSP operations on MCUs without a hardware FPU.

Formulas:

• Scale Factor: 2^n
• Fixed-Point Value: Round(Float * 2^n)
• Float equivalent: Fixed_Value / 2^n

Usage: Input the number of integer bits (m) and fractional bits (n), then enter either a floating-point value or a raw integer to convert bidirectionally.

When you need it: Doing DSP, PID or sensor-scaling math on an MCU without an FPU — representing fractions as scaled integers (Q15, Q1.15) so filters and control loops run fast in integer arithmetic.

Worked example: In Q15 (15 fractional bits) 0.75 → 0.75 × 32768 = 24576 (0x6000). The resolution is 1 / 32768 ≈ 3.05e-5 and the representable range of Q1.15 is [−1.0, +0.99997].

Tips & gotchas:

• Multiplying two Qn values gives a Q2n result — shift right by n to renormalise back to Qn.
• Guard against overflow: accumulate in a wider type (e.g. 32-bit for Q15 products) or use saturating math.
• Q15 cannot represent exactly +1.0; scale your coefficients so they stay below full-scale.
• Round before truncating (add half an LSB) to avoid a consistent downward bias in long sums.

Ohm's Law defines the relationship between Voltage, Current, Resistance, and Power in electrical circuits.

Formulas:

• Voltage: V = I * R
• Current: I = V / R
• Resistance: R = V / I
• Power: P = V * I = I^2 * R = V^2 / R

Usage: Enter any two parameters to automatically calculate the remaining two parameters.

When you need it: The everyday sanity check — finding the third of voltage, current or resistance, or the power a part dissipates, before you pick a resistor wattage or a wire gauge.

Worked example: 5 V across 220 Ω → I = 5 / 220 = 22.7 mA and P = V² / R = 25 / 220 = 114 mW, so a 1/4 W resistor has comfortable margin.

Tips & gotchas:

• Power has three equivalent forms — P = VI = I²R = V²/R — use whichever two quantities you already know.
• Derate resistor power to about 50% of its rating for temperature and reliability margin.
• Ohm's law applies to linear resistors, not diodes or LEDs — those follow their own V–I curve.
• Copper and most resistors drift with temperature, so hot resistance differs from the datasheet's 25 °C value.

Voltage Dividers reduce a voltage level using a pair of series resistors.

Formulas:

• Unloaded Output: Vout = Vin * (R2 / (R1 + R2))
• Loaded Output: Vout = Vin * (R2_eff / (R1 + R2_eff)) where R2_eff = R2 || Rload
• Thevenin Resistance: Rth = (R1 * R2) / (R1 + R2)

Usage: Input Vin, R1, and R2. Optionally enter Rload to evaluate the loading effect, which drops the output voltage.

When you need it: Scaling a voltage into an ADC range (reading a 12 V battery with a 3.3 V ADC), setting a reference or bias point, or level-shifting a sense line. The subtlety is loading: whatever you connect to the output forms a parallel path with R2 and pulls the voltage down.

Worked example: 12 V input, R1 = 10 kΩ, R2 = 3.3 kΩ → Vout = 12 × 3.3 / (10 + 3.3) ≈ 2.98 V, safely inside a 3.3 V ADC range. The output (Thevenin) resistance is 10k ∥ 3.3k ≈ 2.48 kΩ.

Tips & gotchas:

• Keep the divider's Thevenin resistance well below the load (ADC) input impedance, or the reading sags. For SAR ADCs, aim for a source impedance under ~10 kΩ (often much lower).
• Lower resistor values give a stiffer output but draw more standby current, I = Vin / (R1 + R2); higher values save power but load easily.
• Add a small capacitor across R2 to filter noise into an ADC — it forms an RC low-pass with the divider's output resistance.
• A divider is not a regulator: the output tracks the input and cannot supply real current to a load.

LEDs (Light Emitting Diodes) require a series resistor to limit the current, preventing them from burning out due to thermal runaway.

Formulas:

• Single LED: R = (Vs - Vf) / If
• Series LEDs: R = (Vs - (N * Vf)) / If
• Parallel LEDs: R = (Vs - Vf) / (N * If) (Note: matching Vf is required)

Usage: Input your supply voltage, LED forward voltage, and target current. The tool suggests the closest standard E24 resistor and recommends a safe power rating.

When you need it: Any time you drive an LED from a rail higher than its forward voltage — a 5 V MCU pin, a 12 V supply, or a battery. The LED's forward voltage (Vf) is roughly fixed, so the series resistor is what actually sets the current, and therefore the brightness and lifetime. Skip it and the LED draws uncontrolled current and dies from thermal runaway.

Worked example: 5 V supply, a red LED with Vf = 2.0 V, target 15 mA → R = (5 − 2.0) / 0.015 = 200 Ω. The nearest E24 value is 200 Ω. Power dissipated is I²R = 0.015² × 200 ≈ 45 mW, so a common 1/8 W (125 mW) resistor is more than enough.

Tips & gotchas:

• Vf depends on colour: red ≈ 1.8–2.2 V, green ≈ 2.0–3.0 V, blue/white ≈ 3.0–3.4 V. Use the datasheet Vf at your operating current.
• Round the resistor up to the next standard value — that keeps you under the target current rather than over it.
• Modern indicator LEDs are already bright at 1–5 mA; you rarely need 20 mA. Lower current saves power and heat.
• Series LEDs need a supply above N×Vf; parallel LEDs need matched Vf or an individual resistor per LED.

Resistor Decoders help identify the nominal resistance and tolerance of color-banded through-hole resistors and surface-mount (SMD) chips.

Marking Codes:

• 4-Band: Digit 1, Digit 2, Multiplier, Tolerance
• 5-Band: Digit 1, Digit 2, Digit 3, Multiplier, Tolerance
• SMD: 3-digit (10% standard), 4-digit (1% precision), or EIA-96 codes

Usage: Select the color bands for through-hole resistors or enter the alphanumeric SMD code to decode the resistance immediately.

When you need it: Reading a colour-banded resistor, or going the other way to find the bands and the nearest standard value — for 3-, 4-, 5- and 6-band parts as well as SMD number codes.

Worked example: Brown-black-red-gold = 10 × 100 = 1 kΩ, ±5%. A 4-band's third band is the multiplier; a 5-band adds a third significant digit. An SMD marking 472 means 47 × 10² = 4.7 kΩ.

Tips & gotchas:

• Gold and silver multiplier bands mean ÷10 and ÷100 — that's how sub-ohm values are coded.
• The tolerance band (gold ±5%, brown ±1%) sits slightly apart, which tells you which end to read from.
• Snap the result to the nearest E-series standard value; odd values usually mean you misread a band.
• On SMD parts an R marks the decimal point — 4R7 is 4.7 Ω, not 47.

Operational Amplifiers (Op-Amps) are analog building blocks used to scale, filter, or compare signals.

Formulas:

• Non-Inverting Gain: Av = 1 + (Rf / Rg)
• Inverting Gain: Av = - (Rf / Rg)
• Schmitt Trigger (Non-Inv) Hysteresis: Thresholds at Vth = (Vref * R1 +/- Vsat * R2) / (R1 + R2)

Usage: Select your configuration and input resistor values to calculate gain, output voltage, or Schmitt trigger hysteresis thresholds.

When you need it: Setting an inverting or non-inverting stage's gain and checking the resulting bandwidth against the op-amp's gain-bandwidth product, so your signal isn't quietly rolled off.

Worked example: A non-inverting gain of 11 (Rf = 10 kΩ, Rg = 1 kΩ) built on a 1 MHz GBW op-amp gives a bandwidth of GBW / gain = 1e6 / 11 ≈ 91 kHz. More gain buys less bandwidth.

Tips & gotchas:

• Gain × bandwidth is roughly constant (the GBW product) — trade one directly for the other.
• Slew rate limits large, fast signals independently of GBW; check both for a step or high-amplitude sine.
• Input bias current flowing through the source resistance shows up as an output offset — balance the input resistances.
• Driving a capacitive load can cause ringing; a small series resistor or feedback cap restores stability.

Instrumentation Amplifier (3-op-amp) provides high input impedance and precise differential gain. Enter any 4 of the 5 design variables to solve the fifth.

• Gain: G = (1 + 2·R2/Rgain) · (R4/R3)
• Gain resistor: Rgain = 2·R2 / (G·R3/R4 − 1)

When you need it: Amplifying a small differential sensor signal — a bridge, thermocouple or current-shunt — while rejecting the common-mode noise riding on both inputs, all set by one gain resistor.

Worked example: An AD620-style in-amp sets gain by G = 1 + 49.4k / Rg; for a gain of 100, Rg = 49.4k / 99 ≈ 499 Ω. A 10 mV bridge output then becomes 1 V at the ADC.

Tips & gotchas:

• Common-mode rejection (CMRR) is the whole point for bridge and shunt sensing — check it at your gain and frequency.
• Drive the reference pin from a low-impedance mid-supply for single-supply operation, or CMRR collapses.
• Gain-resistor tolerance maps directly to gain error — use a precision part for accurate scaling.
• Provide a DC return path for the input bias currents (e.g. resistors to the reference) or the output drifts to a rail.

Computes R2, R3, R4 for an inverting or non-inverting amplifier with offset control. Set V2 = 0 if no offset is required. Matches the AllAboutCircuits calculators.

Common: R3 = R1 ,   Vout1 = A·V1 ,   Vout2 = Vout − Vout1

Inverting:

• R2 = −A·R1
• R4 = R3·[((R1+R2)·V2 − Vout2) / (Vout2·R1)]

Non-Inverting:

• R4 = A·R3·(V2 / Vout2)
• R2 = A·(R1+R4)/(R4·R1) − R1

When you need it: Back-solving the feedback pair (Rf/Rg) for a target gain and picking real E-series values that land close to it, for either an inverting or non-inverting stage.

Worked example: Inverting gain −4 needs Rf/Rg = 4: pick Rg = 10 kΩ, Rf = 40.2 kΩ (E96) for −4.02. A non-inverting gain of 4 needs Rf/Rg = 3 → Rf = 30 kΩ, Rg = 10 kΩ.

Tips & gotchas:

• Keep Rg above the source impedance and Rf below ~1 MΩ, or bias current and noise dominate.
• The inverting input is a virtual ground — input impedance equals Rg, unlike the non-inverting case.
• Use 1% (E96) resistors for accurate gain; two 5% parts can stack to several percent of error.
• Add a bias-compensation resistor equal to Rf ∥ Rg at the non-inverting input to cancel bias-current offset.

RC Filters are simple passive networks that attenuate signal components outside a target frequency range.

Formulas:

• Cutoff Frequency (3dB): fc = 1 / (2 * pi * R * C)
• Gain (Vout/Vin): 1 / sqrt(1 + (f / fc)^2) (Low-Pass)
• Phase Angle: - arctan(f / fc) (Low-Pass)

Usage: Input resistance and capacitance to find the cutoff frequency. You can also simulate the filter's gain and phase shift at a specific operating frequency.

When you need it: Anti-aliasing in front of an ADC, smoothing a PWM output into an analog voltage, or knocking down high-frequency noise on a sensor line. The cutoff fc is the −3 dB point, where the signal is attenuated to about 70.7% of its input amplitude.

Worked example: R = 1.6 kΩ, C = 100 nF → fc = 1 / (2π × 1600 × 100e-9) ≈ 995 Hz. A single-pole low-pass rolls off at 20 dB/decade, so a tone at 10 kHz (≈10×fc) is attenuated roughly ten-fold.

Tips & gotchas:

• One RC gives only 20 dB/decade — cascade stages or use an active filter when you need steeper roll-off.
• For PWM→analog, put fc well below the PWM frequency (e.g. fc ≈ f_pwm / 100) to keep ripple low.
• Source and load impedance shift the effective cutoff — keep source resistance ≪ R ≪ load resistance.
• The time constant τ = R × C (≈ 1/(2π·fc)) also sets settling time: about 5τ to reach 99% of the final value.

NE555 Timers are popular analog ICs that generate precise square waves (astable mode) or single-shot pulses (monostable mode).

Formulas:

• Astable Frequency: f = 1.44 / ((R1 + 2 * R2) * C)
• Astable Duty Cycle: (R1 + R2) / (R1 + 2 * R2)
• Monostable Period (Delay): T = 1.1 * R1 * C

Usage: Choose the operating mode, enter your resistor and capacitor values, and view the resulting frequency, period, and duty cycle.

When you need it: Designing an astable oscillator or a monostable one-shot with the classic 555 — an LED blinker, a rough PWM source, a debounce delay, or a simple clock.

Worked example: Astable with Ra = 1 kΩ, Rb = 10 kΩ, C = 10 µF → f = 1.44 / ((Ra + 2Rb) × C) ≈ 6.9 Hz at a duty of (Ra + Rb)/(Ra + 2Rb) ≈ 52%. A monostable pulse is t = 1.1 × R × C.

Tips & gotchas:

• A standard astable duty is always above 50% because it charges through Ra+Rb but discharges through Rb only.
• A diode across Rb (charge path bypassing Ra) lets you reach 50% or below.
• Use a CMOS 555 (LMC555/TLC555) for low supply current, rail-to-rail output and higher frequencies.
• Decouple pin 8 and tie the control pin 5 to ground through 10 nF to keep the thresholds quiet.

Capacitor Transient Response defines how voltage rises or falls across a capacitor as it charges or discharges through a resistor.

Formulas:

• Time Constant: tau (τ) = R * C
• Charging Voltage: Vc(t) = Vs * (1 - e^(-t / τ))
• Discharging Voltage: Vc(t) = V_initial * e^(-t / τ)

Usage: Input supply voltage, resistance, and capacitance to calculate the time constant and watch how the voltage evolves over key time milestones (e.g. 99% charge at 5τ).

When you need it: Computing RC charge or discharge time to a target voltage — power-on delays, soft-start, debounce, or sizing a hold-up capacitor for a brief supply dropout.

Worked example: R = 10 kΩ, C = 100 µF → τ = RC = 1 s. Charging reaches 63.2% of the supply in one τ and ~99% in 5τ = 5 s. To hold a rail above Vmin through a dropout, C ≈ I × t / ΔV.

Tips & gotchas:

• Five time constants is "fully" charged (99.3%); design timing around τ, not a vague "instant".
• Real capacitors have ESR (which heats under ripple) and wide tolerance — electrolytics run ±20% and age.
• Derate the voltage rating to about 50% of the working voltage for lifetime, especially on electrolytics.
• Class-2 ceramics (X7R/Y5V) lose capacitance with DC bias and temperature — the applied value can be far below the marking.

CRC (Cyclic Redundancy Check) is an error-detecting code based on binary polynomial division, widely used in storage devices and networks.

Common Polynomials:

• CRC-8 (SMBus): x^8 + x^2 + x + 1 (0x07)
• CRC-16 (Modbus): x^16 + x^15 + x^2 + 1 (0x8005)
• CRC-32 (Ethernet): 0x04C11DB7

Usage: Select either ASCII text or Hexadecimal bytes input, choose your target polynomial, and view the calculated CRC checksum instantly.

When you need it: Computing a CRC over a byte string to compare against the value a device or protocol reports, while bringing up a link or chasing an intermittent corruption bug.

Worked example: The CRC-32 of the ASCII string "123456789" is 0xCBF43926, and CRC-16/Modbus of the same string is 0x4B37 — the standard check values every implementation should reproduce.

Tips & gotchas:

• Two CRCs of the "same" width can still differ — the polynomial, init value, and bit-reflection must all match.
• Hex input must be whole bytes; a stray nibble shifts every subsequent byte and changes the result.
• Modbus RTU sends its CRC-16 low byte first (little-endian on the wire); check byte order before comparing.
• A matching CRC means "very probably intact", not "authentic" — it is not a signature.

Watchdog Timers prevent system lockups by resetting the MCU if the firmware fails to "kick" or reload the timer before it expires.

Formulas:

• IWDG Timeout: Timeout = (4 * 2^PR * RLR) / LSI_Clock
• WWDG Timeout: Timeout = (4096 * 2^WDGTB * (T - 63)) / PCLK1

Usage: Choose your watchdog type. Set the prescaler and reload values to find the exact timing constraints for refreshing your watchdog safely.

When you need it: Recovering an embedded system from firmware hangs — stuck loops, deadlocks, corrupted state — out in the field where nobody can press reset. The watchdog resets the MCU automatically unless your code "kicks" (reloads) it within the timeout window.

Worked example: STM32 IWDG with LSI ≈ 32 kHz, prescaler PR = 4 (÷64) and reload RLR = 1000 → Timeout = (4 × 2⁴ × 1000) / 32000 = 2.0 s. Kick it at least every ~1.5 s to leave margin against jitter.

Tips & gotchas:

• Set the timeout to roughly 1.5–2× your longest legitimate loop: too short causes false resets, too long slows recovery.
• Kick the watchdog from one place in your main loop — never scatter kicks across interrupts, or a hung main loop still gets refreshed and the watchdog is useless.
• STM32 IWDG runs off the independent LSI oscillator (survives a main-clock failure); WWDG runs off PCLK1 and adds a window — kicking too early also triggers a reset.
• The LSI frequency has a wide tolerance (≈ ±5–10%); design your kick interval with that margin in mind.

I2C (Inter-Integrated Circuit) uses open-drain lines requiring pull-up resistors to pull the bus high when devices release the lines.

Formulas:

• Rp (min): (Vdd - Vol) / Iol
• Rp (max): Rise_Time / (0.8473 * Cb)

Usage: Select the speed mode (e.g., Standard or Fast Mode) and input your bus voltage and total bus capacitance to calculate the valid range for pull-up resistors and I2C timing register values.

When you need it: Sizing I2C pull-up resistors so the rising edge meets the bus spec at your total capacitance, or fixing rounded-off edges and NACKs on a long or heavily loaded bus.

Worked example: 400 kHz Fast-mode with 200 pF of bus capacitance and a 300 ns rise-time limit gives Rp_max = tr / (0.8473 × C) = 300e-9 / (0.8473 × 200e-12) ≈ 1.77 kΩ. The sink-current floor is Rp_min = (Vdd − 0.4) / 3mA = (3.3 − 0.4) / 3e-3 ≈ 0.97 kΩ, so ~1.5 kΩ sits safely in between.

Tips & gotchas:

• Every extra device and centimetre of trace adds capacitance, which forces a smaller pull-up to keep the rise time in spec.
• Too-small a pull-up violates the 3 mA (Fast-mode) sink limit and the low-level output voltage; too large slows the edges into NACK territory.
• Standard-mode (100 kHz) allows a 1000 ns rise time, so it tolerates much larger pull-ups on the same bus.
• For very long buses use a bus buffer/accelerator (e.g. active pull-up) rather than fighting RC with ever-smaller resistors.

Number Base Conversion is essential for translating hex values, binary flags, and decimal numbers during debugging.

Conversions:

• Hexadecimal: Base 16 (0-9, A-F)
• Decimal: Base 10 (0-9)
• Binary: Base 2 (0-1)
• Octal: Base 8 (0-7)

Usage: Type in any field, and the other fields will instantly convert the value. It also counts the active (set) bits (Hamming weight).

When you need it: Reading hex register dumps, decoding binary flag fields, or converting between decimal, hex, binary and octal while cross-referencing a datasheet and a debugger.

Worked example: 0xB4 = 1011 0100b = 180 dec = 0264 oct. Each hex digit maps to exactly 4 bits (one nibble), so a byte is always two hex digits — handy for reading memory dumps at a glance.

Tips & gotchas:

• Group binary digits in nibbles (1011 0100) to read them against hex without counting.
• Whether a value is "negative" depends on the word width you assume — 0xFF is 255 as unsigned 8-bit but −1 as signed 8-bit (two's complement).
• Mind prefixes: 0x = hex, 0b = binary, a leading 0 = octal in C.
• Widening a signed value sign-extends (copies the top bit); widening unsigned zero-extends.

LC Resonance occurs when inductive and capacitive reactances cancel each other out, making the circuit act as a bandpass or bandstop filter.

Formulas:

• Resonant Frequency: f0 = 1 / (2 * pi * sqrt(L * C))
• Series Quality Factor: Q = sqrt(L / C) / R
• Parallel Quality Factor: Q = R * sqrt(C / L)

Usage: Enter your Inductance (L) and Capacitance (C) to find the resonance point and characteristic impedance.

When you need it: Finding the resonant frequency of an LC tank for a filter, oscillator or matching network, plus its characteristic impedance for setting the loaded Q.

Worked example: L = 10 µH, C = 100 pF → f = 1 / (2π√(LC)) ≈ 5.03 MHz. The characteristic impedance is Z0 = √(L/C) = √(1e5) ≈ 316 Ω.

Tips & gotchas:

• Frequency scales as 1/√(LC) — to halve it, quadruple either L or C.
• Loaded Q sets bandwidth: BW = f / Q, so a high-Q tank is narrow and sharp.
• Stray board capacitance and lead inductance shift the real resonance — expect to trim in hardware.
• Use NP0/C0G capacitors for a stable, low-drift tank; class-2 dielectrics move with temperature and bias.

BJT (Bipolar Junction Transistor) Voltage Divider Bias provides a stable operating Q-point (collector current and voltage) independent of temperature-induced beta variations.

Formulas:

• Thevenin Voltage: Vth = Vcc * (R2 / (R1 + R2))
• Thevenin Resistance: Rth = R1 || R2
• Collector Current: Ic = (Vth - Vbe) / (Re + Rth/beta) (assuming Vbe ≈ 0.7V)
• Vce Voltage: Vce = Vcc - Ic * (Rc + Re)

Bias State & Stability: Active (Linear) is the amplifier region; Saturated (Vce ≈ Vce_sat) and Cutoff are switch states. The Stability factor S shows how much Ic drifts with β/temperature — a smaller S (use a larger Re) means a more stable bias.

Usage: Input supply voltage, resistors, and transistor gain (beta) to determine the DC bias state: Active (linear), Saturation, or Cutoff.

When you need it: Setting the DC operating point of a common-emitter amplifier with a base voltage divider and an emitter resistor, so the bias stays put over temperature and transistor spread.

Worked example: Vcc = 12 V, target Vc ≈ 6 V at Ic = 1 mA → Rc = 6 kΩ; choose Ve ≈ 1.2 V → Re = 1.2 kΩ, so the base sits at Ve + 0.7 = 1.9 V set by a stiff divider.

Tips & gotchas:

• Make the divider current about 10× the base current so β spread barely moves the bias point.
• The emitter resistor gives DC negative feedback — that's what stabilises Ic against temperature.
• Bypass Re with a capacitor to restore AC gain without losing the DC stability.
• Keep Vce comfortably above saturation across temperature, or the stage clips and distorts.

Decibels (dB) are logarithmic units expressing ratios of power or voltage. dBm expresses absolute power relative to 1 milliwatt.

Formulas:

• Relative Power: dB = 10 * log10(P2 / P1)
• Relative Voltage: dB = 20 * log10(V2 / V1)
• Absolute Power (dBm): dBm = 10 * log10(Power_mW / 1mW)
• Power (mW): Power_mW = 10^(dBm / 10)
• Watts & dBW: W = mW / 1000, dBW = dBm − 30
• RMS voltage over impedance R: P = Vrms² / R → Vrms = √(P · R) (default R = 50 Ω)

Usage: Switch modes and fill in any field. The absolute-power group converts between dBm, mW, W, dBW, and Vrms (across the reference impedance) bidirectionally — enter any one and the rest update.

When you need it: Converting between linear ratios, dB, and absolute dBm power — stacking RF gains and losses, reading a link budget, or translating audio and sensor levels.

Worked example: 0 dBm = 1 mW and +30 dBm = 1 W. A 2× power ratio is +3 dB; a 2× voltage ratio is +6 dB. Feed −10 dBm into a 20 dB amplifier and you get +10 dBm = 10 mW.

Tips & gotchas:

• Power uses 10·log₁₀; voltage, current and field quantities use 20·log₁₀ — mixing them is the classic error.
• dBm is absolute (referenced to 1 mW); plain dB is a relative ratio with no fixed reference.
• +3 dB ≈ double the power, +10 dB = 10× — handy for mental math.
• Add and subtract gains/losses in dB along a chain; never multiply them.

Battery Life Estimation projects the operating lifetime of an embedded system, factoring in battery configuration and circuit efficiency.

Formulas:

• Parallel Capacity: Total_Capacity = Single_Capacity * N_Parallel
• Estimated Runtime (hours): Total_Capacity * (Efficiency / 100) / Load_Current
• Self-Discharge: Capacity_Remaining = Initial * (1 - Rate_per_Month)^Months
• Avg Current (duty): I_avg = Σ (t_k / Σt) × I_k
• Modes: Simple (single I), Advanced (Sleep/Active), Most Advanced (Sleep/Collect/Process/Transmit)

Usage: Input battery capacity, average load current, regulator efficiency, and parallel count to estimate operational life.

When you need it: Estimating how long a battery lasts from its capacity and the load's average current, including derating for high-drain loads and duty-cycled MCUs.

Worked example: A 2000 mAh pack at a 50 mA average draw lasts 2000 / 50 = 40 h in the ideal case. Real runtime is capacity × derate / I_avg, so include sleep current in the average.

Tips & gotchas:

• Use a true duty-weighted average current — a device that sleeps 99% of the time is dominated by sleep draw.
• Peukert's law cuts effective capacity as discharge rate rises; a "2000 mAh" cell delivers less at high current.
• Cold temperature and end-of-life ageing both reduce usable capacity — budget margin.
• For long standby, self-discharge and the regulator's quiescent current can exceed the load itself.

Switching Regulators transfer energy dynamically using switches and an inductor to step voltage up or down with high efficiency.

Formulas:

• Buck Duty Cycle: D = Vout / Vin
• Boost Duty Cycle: D = 1 - (Vin / Vout)
• Buck L(min): (Vin - Vout) * D / (f * Ripple_Current)

Usage: Select Buck or Boost mode. Input Vin, Vout, maximum load current, and switching frequency to compute required inductance (L) and output capacitance (C) values.

When you need it: Picking the duty cycle and inductor, and estimating efficiency, for a switching regulator that steps voltage down (buck), up (boost) or either way (buck-boost).

Worked example: A 12 V→5 V buck runs at D = Vout/Vin = 0.42. Inductor ripple is ΔIL = (Vin − Vout) × D / (f × L); at 500 kHz with L = 10 µH, ΔIL = 7 × 0.42 / (500e3 × 10e-6) ≈ 0.59 A.

Tips & gotchas:

• Size the inductor for about 30% ripple current, and make sure its saturation rating exceeds the peak.
• Higher switching frequency shrinks L and C but adds switching loss and EMI.
• A boost can't fully disconnect its output — input feeds through the inductor and diode even when off.
• Keep the switching-node loop small and the input/output caps close to the IC for clean operation.

Temperature Sensors like NTC Thermistors (nonlinear resistance) and PT100 RTDs (linear resistance) require specialized equations to translate resistance measurements into degrees.

Formulas:

• NTC Beta Equation: 1/T = 1/T25 + (1/B) * ln(R / R25) (T in Kelvin)
• PT100 RTD (Linear approximation): T = (R - 100) / 0.385

Usage: Convert temperature units dynamically, or input thermistor parameters (R25, Beta) and measured resistance to solve for temperature.

When you need it: Converting between °C, °F and K, and translating a thermistor, RTD or thermocouple reading into a temperature in firmware.

Worked example: 100 °C = 212 °F = 373.15 K. An NTC thermistor follows the Beta equation, while a Pt100 RTD reads 100 Ω at 0 °C and rises about +0.385 Ω/°C.

Tips & gotchas:

• NTC thermistors are strongly nonlinear — use the Beta or Steinhart-Hart model, never a straight line, over a wide range.
• RTDs are nearly linear but low-sensitivity, so lead resistance and excitation current matter.
• Thermocouples measure a difference and need cold-junction compensation to give an absolute reading.
• Excitation current self-heats the sensor; keep it small or account for the offset.

Checksums are simple mathematical algorithms used to verify the integrity of transmitted data packets.

Algorithms:

• XOR (BCC): Byte_1 ^ Byte_2 ^ ... ^ Byte_N
• Sum 8-bit: Sum(Bytes) % 256
• Two's Complement Sum: 256 - (Sum(Bytes) % 256)

Usage: Enter ASCII text or Hex bytes. The tool calculates XOR, Sum8, Sum16, Two's complement, LRC, and basic CRCs simultaneously to assist in protocol decoding.

When you need it: Verifying a firmware image or packet payload with a simple additive, two's-complement or XOR checksum before trusting it — the lightweight integrity check on countless serial protocols and hex files.

Worked example: An 8-bit two's-complement checksum of {0x10, 0x20, 0x30}: sum = 0x60, checksum = (−0x60) & 0xFF = 0xA0, so (sum + checksum) & 0xFF = 0x00. Intel HEX records use exactly this scheme.

Tips & gotchas:

• Additive and XOR checksums catch single-byte errors but miss byte reordering and many multi-bit errors — use a CRC when you need real coverage.
• Define whether the checksum byte is itself included in the sum; both conventions exist.
• For 16/32-bit sums, pin down endianness and any carry/one's-complement folding (as in the IP/UDP checksum).
• Specify the initial value and any final XOR so both ends compute the same result.

PCB Trace Calculators assist in designing trace dimensions for target impedance matching or current carrying limits.

Formulas:

• Microstrip Impedance (IPC-2141): Z0 = (87 / sqrt(Er + 1.41)) * ln(5.98 * h / (0.8 * w + t))
• Trace Width for Current (IPC-2221): Area (sq mils) = (Current / (k * Temp_Rise^b))^(1/c), then Width = Area / (Thickness * 1.378)

Usage: Fill in the substrate dielectric constant, copper weight, and current to calculate matched impedance traces or high-current power rails.

When you need it: Sizing a PCB trace for a given current (by allowable temperature rise) or for a target controlled impedance, following the IPC-2221 rules.

Worked example: An IPC-2221 external trace in 1 oz copper carrying 2 A with a 10 °C rise needs about 0.5 mm of width; thicker copper or a smaller allowed rise lets you go narrower.

Tips & gotchas:

• Internal traces need roughly twice the width of external ones for the same current — they cool poorly.
• Copper weight (0.5/1/2 oz) sets the thickness that goes into the current calculation.
• Vias and connectors are thermal chokepoints; add copper or multiple vias where current concentrates.
• Current-carrying width and controlled-impedance width are separate goals — solve each, then take the wider.

In 32-bit embedded systems (like ARM Cortex-M), the compiler aligns member variables to their natural boundaries. This can introduce invisible padding bytes (waste) if members are declared in an inefficient order.

Alignment Rules:

• char / uint8_t: 1-byte alignment
• short / uint16_t: 2-byte alignment
• int / float / pointer: 4-byte alignment

How to Optimize:

Sort your struct members by size in descending order (largest types first). This minimizes padding waste to 0%.

Try This Example (Copy & Paste to Visualizer):

uint8_t status;
uint32_t timestamp;
uint8_t mode;

uint32_t timestamp;
uint8_t status;
uint8_t mode;

C Struct Alignment represents how compilers lay out variables in memory. 32-bit MCUs (like ARM Cortex-M) align variables to their natural boundaries, inserting padding bytes (waste) if declarations are unoptimized.

Alignment Rules:

• char / uint8_t: 1-byte alignment
• short / uint16_t: 2-byte alignment
• int / float / pointer: 4-byte alignment
• union: Starts at offset 0, aligned to maximum member alignment
• bit-field: Packed into base type containers

Optimization: Sort your structure members by size in descending order (largest first) to minimize compiler-introduced padding to 0%.

When you need it: Laying out a C struct for a packet, register block or shared memory, and wondering why sizeof is bigger than the sum of the members — or chasing a hard fault from an unaligned access.

Worked example: struct { char a; int b; char c; } on a 4-byte-align target lays out as a@0, pad@1-3, b@4, c@8, pad@9-11 → sizeof = 12, not 6. Reorder to { int b; char a; char c; } and it packs to sizeof = 8.

Tips & gotchas:

• Order members largest-to-smallest to minimise padding without any packing pragma.
• #pragma pack (or __attribute__((packed))) gives a wire-exact layout, but reading a misaligned member can fault or run slowly on Cortex-M0 and other strict-align cores.
• Natural alignment usually equals the type's own size; a struct's alignment is that of its widest member.
• Don't take the address of a packed member and dereference it as an aligned pointer — copy the bytes instead.

SI vs IEC Standards: Storage vendors specify drives in decimal SI units (1 KB = 1000 B), whereas microcontrollers and operating systems measure RAM/Flash in binary IEC units (1 KiB = 1024 B). This results in a ~2.4% discrepancy at the KB level, rising to ~7.3% at the GB level.

Transmission Time: Calculated as Time = Bits / Baud Rate. For UART, 1 byte is calculated as 10 bits (1 start bit, 8 data bits, 1 stop bit) due to framing overhead.

ADC Buffer Fill Time: Calculated as Time = Total Bytes / (Sample Rate × Bytes Per Sample). This helper predicts when a DMA memory block will trigger a Half-Complete or Transfer-Complete interrupt.

When you need it: Sizing a firmware image against available flash, or working out how long a buffer takes to transmit at a given baud rate or link speed.

Worked example: 256 KiB = 262144 bytes over a 115200 bps UART (8N1 = 10 bits/byte) takes 262144 × 10 / 115200 ≈ 22.8 s. Note KiB (×1024) vs KB (×1000): 256 KiB = 262144 B but 256 KB = 256000 B.

Tips & gotchas:

• Memory (flash/RAM) is binary — KiB/MiB in powers of 1024; link throughput is usually decimal kb/s and in bits.
• 8N1 UART framing adds start+stop bits, so effective byte rate is baud/10, ~25% overhead.
• Real links lose more to protocol framing, ACKs and retries — treat the raw figure as a best case.
• Watch the bit-vs-byte factor of 8: 1 MB/s ≈ 8 Mbit/s.

AWG Diameter Formula (ASTM B258): d = 0.127 × 92^((36-AWG)/39) mm. The cross-sectional area is A = (π/4) × d².

Copper Temperature Correction: Copper resistivity increases with temperature. The formula applied is ρ_T = ρ_20 × (1 + α(T - 20)) where ρ_20 = 1.7241 × 10^-8 Ω·m and α = 0.00393 / °C.

Voltage Drop: V_drop = I × R_total where R_total is calculated for the round-trip wire length (2 × One-Way Length).

Safety & Drop Rating grades the drop %: <3% PASS, 3–5% WARNING, >5% FAIL. A FAIL means the drop is too large (load under-voltage & wire heating) — pick a thicker wire (lower AWG number), shorten the run, or raise the supply voltage.

When you need it: Choosing a wire gauge for a current and run length, then checking the resulting voltage drop and self-heating before you commit to a harness.

Worked example: 18 AWG is about 0.82 mm² and ~2.3 mΩ/ft. Carrying 5 A over a 10 ft round trip (20 ft of copper) drops 5 × 0.046 Ω ≈ 0.23 V.

Tips & gotchas:

• Three AWG numbers lower doubles the copper area and roughly halves the resistance.
• Size for both ampacity (heating) and voltage drop — on long runs the drop is usually the tighter limit.
• Bundling wires and higher ambient temperature both derate the safe current.
• Count the full loop length (out and back) when computing drop, not just the one-way distance.

Microstrip Impedance Formula (IPC-2141):

Z₀ = (87 / sqrt(ε_r + 1.41)) × ln(5.98h / (0.8w + t)) Ω

This equation yields highly accurate matching predictions for typical PCB dielectric substrates (like FR-4) when trace dimensions are in the range of 0.1 < w/h < 3.0.

Impedance Match Status compares Z₀ to the 50 Ω RF standard: <1Ω Optimal, ≤5Ω Good, otherwise mismatch (needs a matching network). Widen the trace or reduce dielectric height to lower Z₀.

When you need it: Computing the characteristic impedance and propagation delay of a microstrip or stripline trace when you need a controlled-impedance route (USB, RF, high-speed digital).

Worked example: On FR-4 (εr ≈ 4.3), a 50 Ω microstrip is roughly 1.8× as wide as the dielectric is thick, and propagation delay is about 6 ps/mm (effective εr ≈ 3).

Tips & gotchas:

• Route over a solid, unbroken reference plane; a gap under the trace ruins the impedance and radiates.
• Microstrip's effective εr sits between air and the laminate because part of the field is in air.
• Either keep the trace short relative to a wavelength/rise-time or terminate it properly.
• Er and stackup tolerances shift impedance — get the actual stackup from your fabricator before finalising widths.

Sallen-Key 2nd-Order Cutoff Frequency:

f_c = 1 / (2 × π × sqrt(R₁ × R₂ × C₁ × C₂))

Quality Factor (Q)LP: Q = sqrt(R₁R₂C₁C₂) / (C₂(R₁ + R₂)). This Q-factor determines the shape of the transition band:

• Bessel (Q = 0.577): Best linear phase, minimal pulse overshoot but slow attenuation.
• Butterworth (Q = 0.707): Maximally flat passband response (no ripple) and sharp roll-off.
• Chebyshev (Q > 0.707): Sharpest attenuation slope but introduces amplitude ripples in the passband.

When you need it: Designing a second-order Sallen-Key low- or high-pass stage — ADC anti-aliasing, audio tone shaping, or sensor smoothing — by choosing R and C for a cutoff and Q.

Worked example: A Butterworth (Q = 0.707) low-pass at fc = 1 kHz with equal R = 10 kΩ needs C = 1/(2π × fc × R) ≈ 15.9 nF; the two capacitor values then set the Q.

Tips & gotchas:

• Q sets the peaking: 0.707 is maximally flat (Butterworth); higher Q peaks near fc and rings on transients.
• Cascade identical stages for steeper roll-off (4th order = two 2nd-order sections with the right Qs).
• The op-amp's GBW must comfortably exceed fc × gain × Q, or the response droops early.
• Use 1% resistors and C0G/NP0 capacitors — loose parts move both fc and Q noticeably.

CAN (Controller Area Network) bit timing splits one bit time into four segments: Sync_Seg, Prop_Seg, Phase_Seg1, and Phase_Seg2. The sample point is the time at which the bus level is read.

Timing Segment Formulas:

• Total TQ: 1 + Prop_Seg + Phase_Seg1 + Phase_Seg2 (or 1 + TS1 + TS2 where TS1 = Prop_Seg + Phase_Seg1)
• Baud Rate: Clock / (BRP * Total_TQ)
• Sample Point (%): (1 + Prop_Seg + Phase_Seg1) / Total_TQ * 100

Usage: Input the peripheral clock frequency, target baud rate, and desired sample point. The solver automatically searches for the best timing registers that minimize sample point error and fit the hardware limits.

When you need it: Bringing up bxCAN/FDCAN on an STM32, or an MCP2515, and needing to hit an exact bus bit rate (e.g. 500 kbit/s) with a sample point that matches every other node on the bus. Get it wrong and the node throws error frames, goes bus-off, or silently drops messages — one of the most common CAN bring-up problems.

Worked example: 36 MHz APB clock, 500 kbit/s, 87.5% sample point → 8 total time quanta with BRP = 9 gives 36e6 / (9 × 8) = 500 kbit/s. With TS1 = 6 and TS2 = 1, the sample point is (1 + 6) / 8 = 87.5%.

Tips & gotchas:

• CiA recommends a sample point of 87.5% for bit rates up to 800 kbit/s and 75% for 1 Mbit/s.
• Keep SJW ≤ min(Phase_Seg1, Phase_Seg2); a larger SJW tolerates more oscillator drift between nodes.
• All nodes must agree on bit rate and roughly on sample point — mixed sample points reduce noise margin.
• STM32 and MCP2515 number their timing segments differently; always cross-check the exact register fields in your datasheet.

Endianness refers to the sequential order in which bytes of data are stored in computer memory.

Formulas & Swaps:

• Big Endian (ABCD): Most significant byte is stored at the lowest memory address.
• Little Endian (DCBA): Least significant byte is stored at the lowest memory address (common in ARM Cortex-M, x86).
• Mid-Little Endian (BADC): Swaps adjacent pairs of bytes (half-word swap).
• Mid-Big Endian (CDAB): Swaps 16-bit half-words within a 32-bit word.

Usage: Type a hex sequence. The tool will parse, pad it to byte alignment, decompose it into a visual byte array block, and output the swapped representations instantly.

When you need it: Exchanging multi-byte values between a little-endian MCU and a big-endian ("network order") protocol, or reading a sensor that ships its data MSB-first.

Worked example: 0x12345678 in little-endian memory is the byte sequence 78 56 34 12; big-endian is 12 34 56 78. A 16-bit swap is (x >> 8) | (x << 8); htonl() byte-swaps a 32-bit value on a little-endian host.

Tips & gotchas:

• Most MCUs (ARM Cortex-M, AVR, x86) are little-endian; TCP/IP and many fieldbuses are big-endian.
• Use compiler builtins like __builtin_bswap32 — they compile to a single REV instruction on ARM.
• Only multi-byte scalar fields need swapping; byte arrays and ASCII strings are already in order.
• Bit order within a byte is a separate question from byte order — don't conflate the two.

7-Segment Displays: Layouts map LED segments `a` through `dp` to specific bits. In Common Cathode systems, bits are Active-High (1 = ON). In Common Anode systems, bits are Active-Low (0 = ON). Supported orders include LSB-first (bit 0 is `a`) and MSB-first (bit 7 is `a`).

Character LCD custom graphics: Renders custom glyphs to CGRAM of standard HD44780 displays. The $5 \times 8$ matrix splits each row into 5 bits. The left pixel is Bit 4 (0x10) and the right pixel is Bit 0 (0x01).

Drag Interaction: On the $5 \times 8$ LCD Matrix editor, click and drag to paint, or start from an active pixel to erase blocks continuously like a mouse brush.

When you need it: Driving a 7-segment display or an HD44780 character LCD from firmware — working out which segment bits light which character before you write the lookup table.

Worked example: On a common-cathode 7-segment with segments a…g = bits 0…6, the digit "3" lights a,b,c,d,g → 0b1001111 = 0x4F, and "0" lights a,b,c,d,e,f → 0x3F.

Tips & gotchas:

• Common-anode displays invert the polarity — the segment bit pattern is the bitwise complement of the common-cathode one.
• Segment-to-bit order depends on your wiring; build the lookup table for your board, don't assume a-to-g = 0-to-6.
• HD44780 custom glyphs live in CGRAM — 8 characters of 5×8 pixels each.
• Multiplex digits faster than ~60 Hz per digit, or the display visibly flickers.